PCIe Lane Margining
PCIe lane margining is a receiver-based diagnostic feature introduced in PCIe 4.0 that measures signal integrity by shifting the receiver’s sampling point in time and voltage while monitoring error rates to determine timing and voltage margins of each lane. LMing can only be performed at speeds higher than 16 GT/s and in L0 state. Monitor error rate while moving sampling points - Horizontal(Timing marging) and Vertical(Voltage margin). LMing measures how far left/right(timing margin) and how far up/down(voltage margin) before errors appear. On retimers, to perform LMing Control SKP Ordered Set, is used to send margining commands and to reveive margin values/status. Margining Measures Used to detect Timing_Margining UI (Unit Interval) margin Jitter ISI Retimer alignment issues Voltage_Margining Signal amplitude margin Attenuation Crosstalk Weak drivers 1. La...